Here’s a photo of the second board, with only the CPLD and surface mount capacitors soldered down by my friend John D:

There are other photos of both boards in the same album.

The next step for the second board will be to install the bus connector, 3.3V regulator and capacitors, and 20 MHz oscillator, and start testing the CPLD, verifying that all the I/Os I use work properly.

I’ll try to gather up some of the stuff I’ve tweeted and write it up here, but here’s an overview of the progress:

• Drew up schematics and PCB layouts for two boards, and submitted both to fab
  • The stage 1 board is a very simple double-sided board that interfaces an 8008 to an FPGA board, which has a Xilinx Artix-7 XC7A100T FPGA, and will make it relatively easy to test my RTL code.
  • The stage 2 board is a smaller four-layer board with a CPLD that interfaces the 8008 to a Z80-style bus. This board took much more effort to lay out. I originally intended to not send it to fab until the stage 1 board was working, but then there would have been no chance of having it back before the end of the month.
• Received the stage 1 board and parially assembled it: photos
• Started debugging the stage 1 board. Errors found so far:
  • I screwed up my Eagle footprint for the DIN 41612 type R male connector. The rows (A, B, C) are correct, but the pin numbering (1 through 32) is reversed. Fortunately the FPGA board uses a symmetric layout so the power rails and ground are still on the correct pins. I just had to redo my Vivado pin constraints file. The 20 MHz oscillator output unfortunately does not end up on one of the FPGA’s global clock inputs, which causes an error, but that can be overridden by another constraint.
  • The data bus signals being driven by the FPGA look funny. While trying to track that down, I discovered that the 74HCT245 data bus buffer was hot enough to burn my finger. There must be one or more shorted outputs, which I now need to track down.

I’ll try to get the LLL DODT monitor running on it, or something similar. It would be nice to have other demo programs, but I haven’t decided what to write.

I reviewed the 8008 datasheet last week. Because the 8008 is a PMOS chip, it requires two power supplies, +5V and -9V, but does not have a ground pin. Effectively it runs on a single 14V power supply, but referenced to +5V. All of the 8008 signals are almost TTL compatible. Vil(max) is 0.8V, which is fine, but Vih(min) is 3.5V, which cannot be guaranteed when driving from bipolar TTL families. However, given how slow the 8008 is, for all pins but the clock, adding a pullup resistor would probably be sufficient to solve that problem.

While most early microprocessors required multiple-phase MOS level (high voltage) clocks, I had forgotten that the 8008 clock inputs have the same electrical requirements as the logic signals.

For my CPU board, I plan to use two SN74AHCT245 8-bit bidirectional bus buffers, one for the data bus and one for the other 8 unidirectional signals. (Bidirectional buffer chips make perfectly fine unidirectional buffers.) Being CMOS, the AHCT family will drive outputs high to nearly 5V, easily meeting the 8008 Vih(min) requirement. The “T” in AHCT indicates that the chip will accept TTL input levels, rather than requiring CMOS levels. The AHCT family is similar to the HCT family, but much faster; the SN74AHCT245 maximum propagation delay is 8.5 ns, vs. 28 ns for the SN74HCT245. Not that the 8008 needs fast timing.

The normal 8008 operates with a 2 us clock cycle. While there are various constraints on the timing of the clock phases, there is some flexibility. There was a speed-binned 8008-1 which was rated to operate with a clock cycle as short as 1.25 us. To operate the 8008-1 at the minimum clock cycle, there is no flexibility in the clock phase timing at all.

I can derive suitable timings for both 2 us and 1.25 us cycles from a 20 MHz clock input, using a counter and decode logic.

The first version of my 8008 CPU board will be designed as a daughterboard to plug into an FPGA evaluation board I have on hand, to let me easily develop the HDL code that I will later put in a CPLD in a later version, which will be much less expensive.

The first 1 1/2 tracks of the disk get loaded into memory from A000..B7FF. That loads the Apple II ROM images into memory from 2000 up. Then it gives the user a chance to change some configuration options. Finally it copies the ROM images into place, does some more hardware configuration, sets the hardware Apple II emulation mode, and jumps into the Apple II monitor ROM.

BMOW Floppy Emu in use on Apple ///

After copying some Apple III floppy images to the MicroSD card, I was pleased to find that it works just fine. I’ve been able to boot SOS 1.3 with Business BASIC 1.23, and Pascal 1.1.

Apple /// running Business BASIC 1.23

Having four non-working drives made me think that perhaps the floppy controller, an integrated part of the Apple III motherboard, might be bad. I switched to my spare motherboard, and didn’t have any different results.

I also have an external Disk III drive. I tried cabling that to the internal drive port, in place of the internal drive, and was able to successfully boot the Apple III Dealer Diagnostics disk. That mostly worked, and I was able to test the RAM and ROM of both motherboards. Both are the later 5V configuration, one with a 5V 256KB memory board, and one with a 5V 128KB memory board (which could easily be expanded to 256KB).

I say “mostly worked” because the drive did give I/O errors trying to load some of the diagnostics, or to display a CATALOG of the diagnostic disk. So really, I have five Apple /// floppy drives that aren’t working properly.

Using a strobe to adjust floppy disk drive spindle motor speed works the same way as the strobe lights on turntables. The drive spindle pulley has a sticker with 50 Hz and 60 Hz stripes. One looks at the stripes illuminated by the strobe light, and if the drive speed is set correctly, the stripes appear to stand still. Otherwise they will appear to rotate in one direction or the other, depending on whether the motor speed is low or high, and at a rate proportional to the speed error. Traditionally a neon lamp was used, powered by AC mains power, at 50 Hz or 60 Hz depending on your locale.

I will use a Harbor Freight LED flashlight, which comes in a two-pack (one with red housing, one with blue), currently on sale for $2.99.  The flashlights use three AAA “heavy duty” zinc-carbon cells. As Richard Ottosen has observed, there is _NO_ current limiting, other than the impedance of the AAA cells, so replacing them with alkaline cells may reduce the life of the LED(s).

I had originally hoped that using only two AAA cells and a very inexpensive boost regulator, I could drive the enable input of the regulator to modulate the LED on and off. However, at 3.0V, the LED draws 73mA, and produces an impressive amount of light. I think I’ll either have to use a “true output disconnect” boot regulator, or use an nFET to switch the power, rather than the boost regulator enable.

Building a self-contained timing stobe light with a boost regulator is beyond the scope of this RetroChallenge project. For now, I’ll just power it from a bench power supply.

The Apple III had one internal floppy drive, and could support up to three external drives. The internal and external drives used the same drive mechanism as the Disk II used on the Apple II, and the same motor control board, but a different analog board. Whereas the Disk II used a 20-position ribbon cable to connect to the interface card, the floppy drives for the Apple III use a 26-position ribbon cable, and there are two connectors and three drive select signals allowing for three external drives to be daisy-chained. Each drive shifts the drive select signals on the daisy chain down, so that the drives don’t need to be configured for their position in the chain. The analog card also has a flip-flop circuit which latches a disk changed signal, not present in the Disk II. The Apple III SOS operating system uses the disk changed indication to ensure that it does not write to the wrong disk even if the user swaps disks at an inopportune time. The disk change signal is derived from detecting an edge on the write-protect sensor.

The usual external floppy drive was known as the Disk III, model number A3M0004, and had a molded plastic housing, unlike the sheet metal housing of the Disk II. However, the earliest external floppy drive for the Apple III was the Disk II for Apple III, model number A3M0003, and did use the same (or nearly the same) sheet metal housing as the Apple II.

Bitsavers has schematics for the Disk II analog card, the Disk III analog card, the UniDisk 5.25 analog card, and the DuoDisk 5.25 analog card. The UniDisk 5.25 was the replacement for the Disk II, and like the Disk III, was in a molded plastic housing. The DuoDisk 5.25 contained two floppy drives in a single housing. The UniDisk and DuoDisk were most commonly used with the Apple IIe.

The suprise discovery was that the UniDisk analog card schematic shows that it has the same disk changed circuit as the Disk III, and that like the Disk III, it has an “Apple II Mode” pin on the connector to disable the disk changed circuit when used on an Apple II, or on an Apple III when running in Apple II emulation mode. When I discovered this, I was excited because I actually have a number of UniDisk 5.25 drives, and would like to use them on the Apple III. I hastily tweeted about my discovery.

Alas, I was almost certainly mistaken. Upon further study, it became apparent that the UniDisk 5.25 analog card schematic on Bitsavers is for a version of the drive that did not make it into production. The schematic and the PCB layout show a 25-pin D-subminiature connector, as used on the Apple III+, but the product as manufactured has a non-standard 19-pin D-subminiature connector, as used on all later Apple floppy drives. The 19-pin connector has only two drive select lines, and does not have the Apple II mode line. I haven’t yet cracked open a production UniDisk 5.25 drive to check, but I’m now fairly confident that will not contain the disk changed circuit needed for use on the Apple III.

However, I then realized that the production DuoDisk 5.25 drive actually _does_ have the 25-pin D-subminiature connector, and a quick check of the pinouts revealed that it appears to match the Apple III+ disk connnector pinout. This causes no end of aggravation to people wanting to use the DuoDisk on an Apple II because it needs a special 19-pin to 25-pin cable, which is very hard to find now.

After tweeting about jumping the gun regarding the UniDisk 5.25, I also tweeted that it was possible that the DuoDisk 5.25 might have the disk changed circuit, and might work directly connected to an Apple III+. I don’t have a DuoDisk 5.25 to test, and I have an Apple III with 26-pin header for the disk connector rather than an Apple III+, so I wasn’t able to test it myself. To my amazement, within a few hours @jrobj_ confirmed that the DuoDisk works on the Apple III+ and does have the disk changed circuit.

It is interesting to note that the DuoDisk schematic shows only a single disk changed detection circuit for both drives, rather than separate circuits for each drive. As a result, if the user changes either diskette, SOS will think that both have been changed.

At the moment the floppy drive of my Apple III isn’t working properly, so I’ll have to fix that or replace it with one of my spares, though the spares aren’t necessarily in working order either. This evening I purchased a two-pack of inexpensive LED flashlights from Harbor Freight, and I plan to modify one, adding a PIC or AVR microcontroller, crystal, and NFET, to make a timing light for adjustment of motor speed. I hope that just adjusting the motor speed will be sufficient to get at least one of my floppy drives working; I don’t presently have a head alignment diskette.

In 1983, I mostly reverse-engineered the version 1, 2, and 3 (no revision letter) of the Infocom ZIP interpreters into source code that could be assembled using Microsoft ALDS on CP/M. Until recently, all that survived of that effort was a printed listing, which my friend Richard had preserved, and returned to me in 2002. I put a scanned PDF of the listing online, and . The listing has false conditionals disabled, so only the code for the version 3 interpreter is seen, with a two-instruction modification I made to display lower case. (Infocom’s 3A interpreter supported 80 column display with lower case on the Apple IIe.)

In the last few weeks, I retyped the source code, converted it to assemble with a modern cross-assembler, added back the conditionals for ZIP versions 1 and 2, and added the code for 3A and 3B. I’ve put it on Github. This source code will be used as the basis for the SOS port of the interpreter.

The display output and keyboard input code will have to be replaced with code that uses the .CONSOLE driver, and the disk I/O code, both for “story file” and save file access will have to be replaced with code that uses the SOS file system calls, which are similar to the ProDOS file system calls used on the Apple II.