Retrochallenge progress

Not only have I not posted any Retrochallenge updates here, but I just noticed that the MariaDB instance was down, for no obvious reason, preventing the blog from working. I started it up again. The real reason for the lack of updates here is that it’s so much faster and easier to tweet about the progress.

I’ll try to gather up some of the stuff I’ve tweeted and write it up here, but here’s an overview of the progress:

  • Drew up schematics and PCB layouts for two boards, and submitted both to fab
    • The stage 1 board is a very simple double-sided board that interfaces an 8008 to an FPGA board, which has a Xilinx Artix-7 XC7A100T FPGA, and will make it relatively easy to test my RTL code.
    • The stage 2 board is a smaller four-layer board with a CPLD that interfaces the 8008 to a Z80-style bus. This board took much more effort to lay out. I originally intended to not send it to fab until the stage 1 board was working, but then there would have been no chance of having it back before the end of the month.
  • Received the stage 1 board and parially assembled it: photos
  • Started debugging the stage 1 board. Errors found so far:
    • I screwed up my Eagle footprint for the DIN 41612 type R male connector. The rows (A, B, C) are correct, but the pin numbering (1 through 32) is reversed. Fortunately the FPGA board uses a symmetric layout so the power rails and ground are still on the correct pins. I just had to redo my Vivado pin constraints file. The 20 MHz oscillator output unfortunately does not end up on one of the FPGA’s global clock inputs, which causes an error, but that can be overridden by another constraint.
    • The data bus signals being driven by the FPGA look funny. While trying to track that down, I discovered that the 74HCT245 data bus buffer was hot enough to burn my finger. There must be one or more shorted outputs, which I now need to track down.
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