Retrochallenge project: an 8008 CPU board

My RC2019/10 project is to design and build a new CPU board using the Intel 8008. The 8008 was Intel’s first 8-bit microprocessor, first announced in April 1972. The 8008 architecture was based on that of the Datapoint 2200.

I’ll try to get the LLL DODT monitor running on it, or something similar. It would be nice to have other demo programs, but I haven’t decided what to write.

I reviewed the 8008 datasheet last week. Because the 8008 is a PMOS chip, it requires two power supplies, +5V and -9V, but does not have a ground pin. Effectively it runs on a single 14V power supply, but referenced to +5V. All of the 8008 signals are almost TTL compatible. Vil(max) is 0.8V, which is fine, but Vih(min) is 3.5V, which cannot be guaranteed when driving from bipolar TTL families. However, given how slow the 8008 is, for all pins but the clock, adding a pullup resistor would probably be sufficient to solve that problem.

While most early microprocessors required multiple-phase MOS level (high voltage) clocks, I had forgotten that the 8008 clock inputs have the same electrical requirements as the logic signals.

For my CPU board, I plan to use two SN74AHCT245 8-bit bidirectional bus buffers, one for the data bus and one for the other 8 unidirectional signals. (Bidirectional buffer chips make perfectly fine unidirectional buffers.) Being CMOS, the AHCT family will drive outputs high to nearly 5V, easily meeting the 8008 Vih(min) requirement. The “T” in AHCT indicates that the chip will accept TTL input levels, rather than requiring CMOS levels. The AHCT family is similar to the HCT family, but much faster; the SN74AHCT245 maximum propagation delay is 8.5 ns, vs. 28 ns for the SN74HCT245. Not that the 8008 needs fast timing.

The normal 8008 operates with a 2 us clock cycle. While there are various constraints on the timing of the clock phases, there is some flexibility. There was a speed-binned 8008-1 which was rated to operate with a clock cycle as short as 1.25 us. To operate the 8008-1 at the minimum clock cycle, there is no flexibility in the clock phase timing at all.

I can derive suitable timings for both 2 us and 1.25 us cycles from a 20 MHz clock input, using a counter and decode logic.

The first version of my 8008 CPU board will be designed as a daughterboard to plug into an FPGA evaluation board I have on hand, to let me easily develop the HDL code that I will later put in a CPLD in a later version, which will be much less expensive.

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