I’ve nearly finished tracing the Pacer control panel interface card schematic. I haven’t yet traced the connections of one NOR gate of the 7425 at position 6A, and one inverter of the 7404 at position 5C. It’s possible that they’re unused.
As with the other Pacer schematics I’ve reverse-engineered, there are probably errors and omissions. The purpose of reverse-engineering this wasn’t necessarily to produce perfect schematics, but to develop enough understanding of the Pacer to diagnose and repair faults, and to design new memory and I/O cards. Considered in that light, the reverse-engineering process has mostly been successful.I say “mostly” because the control panel interface card contains a lot of complex random logic with a lot of flip-flops, the purpose of many of which remain unknown. The CPU and user memory cards, by comparison, are nearly completely understood.
This has allowed me to track down to faults in my Pacer to a single failed DS8833N bidirectional buffer on the user memory card. The fault caused all user memory to read back with the most significant four bits set, and to mirror the RAM at 0000-03ff hex to 2000-23ff hex. I have not yet replaced the chip, but by examination with test equipment I’m certain that’s the problem.
Because the reverse-engineering of the control panel interface card has taken so much longer than expected, I’ll have to leave the construction of a new, higher-capacity memory card for the 2015/07 RetroChallenge.