After quite a few hours with a continuity tester and magnifier, I have the PACER CPU card mostly figured out, and have drawn a schematic . I haven’t identified all of the passive component values, and there are probably other errors and omissions, because I’m not trying for perfection, but rather to understand enough of the machine to repair problems and design a memory upgrade.
The PACE data bus is not fully TTL-compatible, though for read cycles a TTL buffer can drive it, and the PACER uses 74367 hex tristate buffers for that. For address and data output from the PACE, it has PMOS open-drain outputs, so pulldowns are required, but the PACER doesn’t have any. National Semiconductor recommended to use the DS3608N hex MOS sense amplifier without pulldowns, but since the DS3608N data sheet does not indicate that it has internal pulldowns, I don’t really understand how that can work reliably (or at all), though it obviously does.