At present the RAM on the user memory board in the PACER isn’t working correctly; the four most significant bits (D15..D12) are always reading as ones. Since this is true for all four banks of RAM (0000-00FF, 0100-01FF, 0200-02FF, and 0300-03FF), this probably isn’t a failure of one of the RAM chips, but rather of one of the DS8833N bus buffers. Those are fairly uncommon and I don’t think there are any pin- and function-compatible substitutes, so I’ll have to buy some from a broker or an eBay seller.
I’d like to dump the contents of the PACER monitor ROMs and disassemble the code, but at the moment that’s more of a challenge than one might expect.The PACER has two Electronic Arrays EA4900 2Kx8 PMOS masked ROMs on the control panel interface card, providing the ROM monitor. I haven’t been able to find an Electronic Arrays data book, or data sheet for the EA4900. Electronic Arrays was acquired by NEC not too long afterward, but the earliest NEC databooks I can find don’t cover the EA4900. Even though the EA4900 pinout didn’t become a real standard, there were at least a few pin-compatible masked ROMs from other vendors, such as the Mostek MK28000 (data sheet from Mostek 1977 Memory Products Catalog), but it is unclear how closely the electrical and timing characteristics actually match.The ROMs are not easily read because:
- The ROMs are soldered in place, and I’d rather not desolder them.
- The EA4900 has an internal address latch and a pinout totally different than more recent NMOS 2Kx8 ROMs and EPROMs, so even if I did desolder them no normal EPROM programmer can read them.
- Trying to read the monitor ROM by examining its memory addresses from the monitor itself shows only FFFF. I’m not sure whether this is due to code in the monitor ROM, or hardware that prevents user access to the ROM.
- There are home-made resistor networks used for data bus pulldowns soldered directly adjacent to the ROMs, with the resistor bodies essentially in direct contact with the top of the PCB, and these obstruct connecting logic analyzer grabbers to some of the data lines.
In order to read the ROM contents, I’m going to connect a logic analyzer to the ROM address and data lines, and capture data from the front panel, examining C000 then pressing the up arrow button on the keyboard 2047 times to read all of the contiguous addresses up to C7FF.
The control panel interface card is a long card, and normally the user memory card is right in front of it, blocking the use of test clips. I don’t want to remove the backplane again, which would be necessary to remove the card guide for the user memory card as would be required to swap the two. It turns out that the PACER ROM monitor will work fine without the user memory card installed.
I hooked up logic analyzer grabbers to the ROM address, data, AR (address strobe), and output enable signals, as can be seen in this photo. The logic analyzer is an HP/Agilent 16702A with a 16752A 68-channel module with 32M sample memory. I started the analyzer in timing mode, and powered up the Pacer.
In the captured trace, I can see that the monitor code is in a tight loop, probably waiting for a key press. However, apparently after I connected the grabbers, two of them for data lines 4 and 6 apparently fell off or are not making contact, as the analyzer shows that those two data lines are always low, even as I exercise the PACER from the keyboard. I’ll have to pull the card out and try again, which is a tedious task.
I added more photos to the album.