My 1802 model was missing some state transitions necessary for load mode to work properly. Load mode occurs when CLEAR and WAIT are asserted simultaneously. In this mode, DMA operations can occur, but no instructions can execute and no interrupts can be recognized. In my state machine, state_clear_2 would transition to state_dma_in or state_dma_out when in load mode, but when the DMA signals were deasserted, those states would transition to state_fetch or state_interrupt. I added conditionals to return to state_clear_2 if WAIT is still asserted.
Now I need to test load mode, switch debouncing, and the data switch inputs and LED outputs in simulation.
Hi, has the testing been successful? It is about time that the 1802 makes the next step.
From the first CMOS Micro to the first freely available Core that can be implemented into FPGAs.