VHDL switch debouncer for FPGA-Elf

I think I’ve already written VHDL code to debounce switches, but I can’t find it at the moment, so I’ve just written new debouncing code for the FPGA-Elf.  The system clock is divided down to produce a debounce clock of around 1 KHz.  Each debouncer takes as input that clock and a raw switch input, and produced a debounced output.  The debouncer has a one-bit current state, and a four-bit counter.  Whenever the raw input matches the current state, the counter is reset to zero.  When it doesn’t match, the count is incremented, and if the count hits a maximum, the state is toggled.