RetroChallenge RC2017/10 final report

My RetroChallenge RC2017/10 project was to update and improve my FPGA-Elf. The resulting hardware may be seen here:


I have succeeded in accomplishing my main goals for the project, which were:

  1. Update my FPGA-Elf design to use a currently-available, relatively inexpensive FPGA board/module
  2. Design a base PCB for the FPGA-Elf, using only through-hole components, and have it fabricated
  3. Implement CDP1861 PIXIE graphics

I originally wanted the new hardware design to use only currently-manufactured components, which would rule out both the HP 5082-7340 hexadecimal LED displays used by the original Elf and the TI TIL311 hexadecimal LED displays often used in more recent Elf builds.  As an alternative I chose the Liteon LTP-305HR, which is a 5×7 dot matrix LED display, a drop-in replacement for the Monsanto or GI MAN2A or the TI TIL305.

I spent the first week of the RetroChallenge building a breadboard prototype of a six-character display using the LTP-305HR, with serial low-side and high-side drivers, and a MicroBlaze soft-core CPU in the FPGA controlling them. While I got the displays working, there were issues with the drive circuitry resulting in off pixels glowing, though less brightly than on pixels. I also did not like the appearance of the displays as much as the original hexadecimal LED display, so I abandoned the use of 5×7 dot matrix LED displays and proceeded to design my new board to accept either HP 5082-7340 or TI TIL311 displays.

I completed the PCB board designs by October 17th and placed the order for the boards. Due to the rush to get this done, there are a few minor errors in the board design that require some trace cuts and jumps.

While waiting for boards to arrive, I built a second breadboard prototype using the hexadecimal displays, and used it to design my CDP1861-compatible graphic display core. As with my earlier CDP1802-compatible CPU core, it is designed in synthesizable VHDL. There are no vendor-specific constructs except in the top-level Elf design which instantiates a Xilinx PLL clock multiplier.

The printed circuit boards arrived on October 23rd, and I assembled one on the 24th. After fixing one design error and removing one solder bridge, the FPGA-Elf was able to run my dice program.

By October 27th I had the PIXIE graphics fully working, running the PIXIE demo as shown in the July 1977 Popular Electronics article. I also ran my clock program. The FPGA-Elf is currently configured to run at 256 times the speed of an original Elf, so the clock runs at 256x real time. However, the clock display output is somewhat garbled, suggesting that my 1802 core has a previously undetected error.

Almost all of the project was done while I was out of town on a business trip. I returned home on October 28th, and badgered Richard Ottosen into cutting and drilling wood mounting rails for the FPGA-Elf, as seen in the photo. I have not yet done any further work on the hardware, FPGA code, or software.

I have quite a few Post-RetroChallenge tasks:

  1. Fix issue resulting in garbled clock display. (This issue will affect other programs also.)
  2. Publish design documents and source code:
    1. FGPA code for top-level design and CDP1861 graphics core (base Elf design and CDP1802 CPU core are already on github)
    2. Eagle CAD files for schematics and PCB designs
    3. PDF schematics
    4. PCB Gerber and Excellon files
  3. Add MicroSD and TIA-232-F serial port components to the board and test them. The serial port will require two more cuts and jumps, because I forgot to deal with the FPGA not being 5V-tolerant. Note that the MicroSD and serial port were not part of my project objectives; I included them in the PCB layout for future use.
  4. Write a manual, including BOM and assembly instructions (including rework needed for rev 0 main board)
  5. Update main PCB design to correct errors, and order rev 1 main board
  6. Update FPGA code for rev 1 main board
  7. Build and test rev 1 main board
  8. Add UART to FPGA
  9. Write 1802 code to support SD card

I have six extra sets of bare PCBs of the current design which are available for sale. I do not offer kits or assembled units.

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