My VHDL reimplementation of the CDP1861 PIXIE graphics chip is mostly working! This still image looks almost the same as the one from a few days ago:
The difference is that now it’s being generated by the 1802 program (seen in the top 1/4 of the bitmap) actually running, whereas before it was hard-coded into the frame buffer memory to test the output half of my VHDL code.
Since that worked, I decided to try my clock program. Because the 1802 is running 256 times as fast as a normal Elf, I expected the clock to run at over four hours to the minute, and it does, but the graphics is garbled:
It’s possible that my 1802 core isn’t executing some instruction correctly, though it worked well enough to run a number of Forth programs on CamelForth. I’ll debug this using a VHDL simulator to capture a trace of my hardware design from reset to the completion of the first video frame, and a logic analyzer to capture the same from the electrical signals of the Elf II for comparison.