Comments on: Fixed a bug in the FPGA-Elf

By: Eric

Eric — Thu, 15 Dec 2011 21:45:31 +0000

I haven’t released it as open-source yet, mostly because I haven’t gotten around to testing the full instruction set and interrupts. I hope to finish that in January.

The core is cycle-accurate at the machine cycle level, but not at the clock cycle level. The CDP1802 uses eight clock cycles per machine cycle, while my core uses only one clock cycle per machine cycle. This means that the bus interface is not at all similar to the CDP1802. It’s more like a 6502 or 6800 bus.

It should be possible to write a wrapper that interfaces the core to a real CDP1802 bus. Such a wrapper would have have a counter to divide by 8 to get the core clock, generate the TPA and TPB strobes, etc. I haven’t done that yet.

To make the 1802 core work with a VGA monitor, you would need an 1861 core, which I have not completed, and a simple scan-converter to take the 1861 core output, buffer it, and drive the VGA output at normal VGA scan and pixel rates.

By: Dave S

Dave S — Thu, 15 Dec 2011 18:30:20 +0000

Are the VHDL files and any other supporting documentation available for download? I would love to be able to try this at home on my own FPGA demo board. I’m wondering if this is cycle-accurate to the original 1802? Could it be used in conjunction with an 1861, or is a VHDL version of the 1861 available???

My Spartan FPGA board has a VGA output connector on it, what would it take to make things work with an emulated 1861 going to a VGA monitor?

By: juergen_uk

juergen_uk — Fri, 10 Dec 2010 16:01:24 +0000

Hi How could I get hold of the ELF for FPGA?