FPGA-Elf load mode fixed, now can load and run program in simulation

I changed the state machine in my Elf code to something much simpler, based on the observation that in load mode the DMA input cycle *always* is acknowledged immediately, and that I don’t have to wait for the 1802 core state code output to indicate DMA before deasserting the DMA input.

Now I can (in simulation) load a simple program and run it.

This entry was posted in FPGA, RetroChallenge. Bookmark the permalink.

Leave a Reply