My VHDL reimplementation of the CDP1861 PIXIE graphics chip is mostly working! This still image looks almost the same as the one from a few days ago:
The difference is that now it’s being generated by the 1802 program (seen in the top 1/4 of the bitmap) actually running, whereas before it was hard-coded into the frame buffer memory to test the output half of my VHDL code.
Since that worked, I decided to try my clock program. Because the 1802 is running 256 times as fast as a normal Elf, I expected the clock to run at over four hours to the minute, and it does, but the graphics is garbled:
It’s possible that my 1802 core isn’t executing some instruction correctly, though it worked well enough to run a number of Forth programs on CamelForth. I’ll debug this using a VHDL simulator to capture a trace of my hardware design from reset to the completion of the first video frame, and a logic analyzer to capture the same from the electrical signals of the Elf II for comparison.
After removing one solder bridge, cutting one trace, adding one wire*, and changing a few lines in a Xilinx constraints file, My RetroChallenge Elf project has now let me successfully toggle in and run its first simple program, which is my old dice program.
I also learned how to program the FPGA config into the SPI flash on the Cmod-A7 module, so that the Elf is available after every power up. Suprisingly this is more complicated with the newer Xilinx Vivado development software than it was with the older ISE.
I don’t have a tripod here, so I won’t be able to shoot a demo video until the weekend.
* I’m going to claim that having blue wire-wrap wire for the bodge matching the blue of the PCB soldermask is due to good planning. Couldn’t possibly just be a coincidence.
Not everything is installed, but the power supply, data hex LEDs, most of the switches, and the composite video output are working.
The switch for data bit 3 doesn’t work because I wired it to an analog input pin of the Cmod-A7 module, and the FPGA internal pullup isn’t enough when the switch is on (open) to overcome the 2.4K series resistance on the module and bring the signal up to a logic 1.
I just hacked up more VHDL code to get the Elf hexadecimal displays working. I’ve only tested the data displays, but the address should work as well. This probably doesn’t sound like much of an accomplishment, especially compared to my original work on driving six multiplexed 5×7 dot matrix displays, but it’s not quite as trivial as one might expect.
While the original Elf only had two digits of hexadecimal LED display for data, my #retrochallenge FPGA Elf will also have four digits for displaying the address, particularly useful in load mode. While the Xilinx Artix 7 has quite a few I/O pins, the Digilent Cmod-A7 FPGA module only brings out 44 to module pins, and I can’t use 24 of them for the hexadecimal displays.
I originally considered having eight data lines and three each strobe and blanking lines (for the address high, address low, and data, and blanking isn’t really necessary), but I was in a hurry to route the board and it wasn’t as easy as I’d have liked to route two sets of four data lines to alternate digits. To make the board routing easier, I ended up with four data lines, six strobe lines (one per digit), and three blanking lines.
As a result, I had to write a state machine to detect when either the address or data has changed from the previous value, latch the new value, and sequence through updating all six digits.
I haven’t wired up the address displays on the breadboard, but the data displays are working fine. I’m now able to toggle in a short program, such as my dice program, and run it with the expected data display output.
I did test the switches wired to my RetroChallenge project solderless breadboard last night, and they work fine. Today I worked on the monochrome NTSC composite video output.
First I got the video counters working, and generated a frame with fixed data:
The CDP1861 PIXIE timing is used (262 scan lines, 128 scan lines active, 14 bytes per line of which 8 are active). The data byte is fixed.
I was pleasantly surprised that the video timing and voltage levels worked on the first attempt.
The CDP1861 PIXIE uses DMA to read memory and directly shifts the bits out as video. In my design, because the CPU may be run at various speeds, from 1x to 256x the original Elf speed, the PIXIE logic will write bytes into a dual port RAM, and dedicated logic will scan them out as NTSC monochrome video. In this test, the CPU is not hooked up, and the frame buffer data is statically initialized to match the screen shot at the beginning of the July 1977 Popular Electronics article, page 41.
Due to an error in my design, the rightmost pixel column is being displayed on the left. Here’s the image after that error has been corrected:
I still need to hook up the CDP1861 DMA logic to the CPU, so that I can run the actual program, and others. PCBs are still expected to arrive on Tuesday.
Since my PCBs aren’t likely to be here before Tuesday evening, and I’ve abandoned the 5×7 matrix LEDs, I’ve had to throw together a second hardware prototype using the HP 5082-7340 hexadecimal LED displays.
In this photo, it is running a hardware test using a Xilinx MicroBlaze soft core, rather than my 1802 core. I’ve tested the LEDs, but have not yet tested the switches and composite video output. I’ll test those tomorrow, then switch to my 1802 core.
I can’t believe how well fingerprint smudges show up on the switch panel. Yuck! I’m not bothering to clean this one, because I’ll have the new rev of the switch panel when the new PCBs arrive.
Late last night I finished the schematic and PCB layout, and ordered boards. As soon as I woke up this morning I realized that I forgot to deal with the 5V CMOS output of the TIA-232-F receiver feeding the non-5V-tolerant FPGA input. There needs to be either a series resistor or a pair of resistors as a voltage divider. I’ll have to cut that trace and bodge one or two resistors.
I ordered parts from Digi-Key to build two units. Of course, shortly after placing the order I realized that I’d forgotten to order power supplies. It doesn’t require anything too special, just regulated 5V 2A with a 2.1/5.5mm coax plug.
I expect most of the Digi-Key order to arrive on Friday, and the PCBs will likely be here on Monday.
Other stuff I ordered to build the project arrived today:
I have two soldering stations at home, but I’m not there so I had to order a Hakko FX-888D to use here. I also expect to breadboard a few more things, so I ordered five more solderless breadboards, and (not shown) more precut breadboard wires.
Although I got the LTP-305HR dot-matrix LED multiplexing working, it doesn’t look anywhere near as nice as the original HP 5082-7340 or TI TIL311 hexadecimal displays. I’ve decided to drop my original plan to use the LTP-305HR displays, and use the hexadecimal displays instead. Broadcom (previously Avago, previously Agilent, previously HP) does still make similar hexadecimal displays, though without the red filter. They are quite pricey.
I’ve focused on getting the schematic and PCB layout done so that I can order PCBs this week. The switch PCB and switch bezel PCB are only minor tweaks to some I made last year, so those are ready. I’ve got the main board layout nearly completed; I need to add one electrolytic capacitor for bulk bypass, and one 14-pin header for configuration and/or expansion. Here’s an image of the not-quite-complete layout:
The board will accept either the HP 5082-7340 or TI TIL311 displays, using interleaved footprints. The board can be stuffed with just the traditional two digit data display, or can additionally have a four digit address display.
The I/O ports are a USB port (providing JTAG programming and a virtual UART) on the Cmod-A7 FPGA board, a MicroSD card, a TIA-232-F serial port, and an RCA jack for monochrome composite video.