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Category Archives: FPGA
More FPGA-Elf photos and a video
I’ve added some photos of the completed hardware, showing the Avago hexadecimal displays to my FPGA-Elf set. I also shot a brief video showing an LED test, though it is not using the 1802 core. (I got the 1802 core … Continue reading
Posted in FPGA, RetroChallenge
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FPGA-Elf success! Well, mostly.
I got the switches wired up and working, with a little help from Richard Ottosen. I tested the debouncer, which worked. Then I went for broke and loaded the complete Elf system into the FPGA. After a bit more debugging, … Continue reading
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Hexadecimal LEDs wired and working
I’ve wired up the Avago hexadecimal LEDs to the FPGA board and verified that they work with some VHDL test code (not yet tried with the VHDL Elf code). Now I need to wire up the switches. Does anyone have … Continue reading
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FPGA-Elf load mode fixed, now can load and run program in simulation
I changed the state machine in my Elf code to something much simpler, based on the observation that in load mode the DMA input cycle *always* is acknowledged immediately, and that I don’t have to wait for the 1802 core … Continue reading
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Debugging 1802 “load mode”
I threw together a testbench for the Elf, with the switch debouncing disabled. The testbench tries to use load mode to load a program that has an infinite loop setting and clearing the Q flag, which is available as an … Continue reading
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FPGA-Elf progress
I’ve assembled more of the front panel, but still can’t get photos uploaded to flickr. I’ve ordered connectors and ribbon cable from Digikey, and paid for overnight shipping so they should be here on Tuesday. I’ve written a model of … Continue reading
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Implemented CDP1802 “load mode” in VHDL model
My 1802 model was missing some state transitions necessary for load mode to work properly. Load mode occurs when CLEAR and WAIT are asserted simultaneously. In this mode, DMA operations can occur, but no instructions can execute and no interrupts … Continue reading
Posted in FPGA, RetroChallenge
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VHDL switch debouncer for FPGA-Elf
I think I’ve already written VHDL code to debounce switches, but I can’t find it at the moment, so I’ve just written new debouncing code for the FPGA-Elf. The system clock is divided down to produce a debounce clock of … Continue reading
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FPGA-Elf front panel parts arrived from Mouser
My order from Mouser Electronics, fifteen toggle switches, two pushbutton switches, and two hexadecimal LED displays, arrived today. UPS ground shipping from Mansfield, Texas to Denver, Colorado took two days. The Elf only needs eleven toggle switches and one pushbutton … Continue reading
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Installed Xilinx ISE WebPack 12.1 on Fedora 12 x86_64
I’ve moved most of my development activities onto my new notebook, running Fedora 12 x86_64 Linux. Today I installed Xilinx ISE WebPack 12.1 on it. ISE is officially supported on Red Hat Enterprise Linux, but not on Fedora. Fedora is … Continue reading
Posted in FPGA, RetroChallenge
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